The invention relates to amplifier output stages having NPN transistors but no lateral PNP transistors in the AC signal path from the input to the output, and more particularly to a fast, stable NPN push-pull output circuit which can produce output voltage levels close to the positive and negative power supply voltages.
FIG. 1A hereof shows a typical prior art push-pull output circuit including an NPN pull-up transistor 21 having its collector connected to V.sub.DD, its emitter connected to an output voltage conductor 3 on which an output voltage V.sub.OUT is produced, and its base connected by a conductor 22 to the junction between a constant current source 25 and to the anode of a diode 23, the cathode of which is connected to the anode of a diode 24. The cathode of diode 24 is connected by a conductor 2 to the base of a PNP pull-down transistor 20 in a pull-down circuit 20A. The collector of pull-down transistor 20 is connected to ground. A constant current source 25 is connected between conductor 22 and +V.sub.DD. (Note that input voltage V.sub.IN can be applied either to conductor 2 or conductor 22.) FIG. 1B shows that in the push-pull circuit of FIG. 1A the pull-down circuit 20A can include PNP transistor 20 with its collector connected to the base of an NPN pull-down transistor 26 having its emitter connected to ground and its collector connected to output conductor 3. Yet another known output stage is disclosed in U.S. Pat. No. 4,403,200 by Davis.
It has been recognized in the prior art that the circuit shown in FIG. 1B can be diagrammed generally as shown in FIG. 1C, wherein a differential transconductance amplifier 18 has a (-) input coupled by conductor 2 to receive the input voltage V.sub.IN and to the cathode of a single diode 23, the anode of which is connected to conductor 22. The (+) input of differential amplifier 18 is connected by conductor 3 to receive the output voltage V.sub.OUT. The output of differential amplifier 18 is connected to the base of a pull-down NPN output transistor 26 which constitutes pull-down circuit 20A.
Those skilled in the art know that capacitive loading can produce instability of the pull-up and pull-down transistors, especially the NPN pull-down transistor. This is because the gain of the output stage while sinking current is a function of the output load impedance. In the above prior art circuits of FIGS. 1B and 1C the gain-bandwidth product is linearly dependent on the capacitive output load, or more generally, on the load impedance. Consequently, circuit instability can be caused by large capacitive loads, and the resulting oscillations in the output stages of FIGS. 1B and 1C introduce distortion into the output signal. To obtain stable, reliable circuit operation, it is desirable that the voltage gain of the output stage be determined mainly by design parameters, and hence be fairly independent of the load impedance.
Some known high-speed operational amplifiers, such as the assignee's OPA650, use a gain stage that includes a differential NPN input stage followed by "folded cascode" PNP transistors connected to an NPN current mirror. The current mirror then drives a separate, distinct output stage that includes a diamond follower circuit. The details of such an operational amplifier are set forth in the assignee's allowed pending patent application "STABLE BIAS CURRENT CIRCUIT FOR OPERATIONAL AMPLIFIER", Ser. No. 08/710,632, filed Sep. 18, 1996 by Douglas Smith, now U.S. Pat. No. 5,786,729, issued Jul. 28, 1998, incorporated herein by reference. The PNP folded cascode transistors of the gain stage of the above-mentioned OPA 650 operational amplifier are "vertical" PNP transistors, which cannot be provided in typical inexpensive bipolar integrated circuit manufacturing processes.
Only lateral PNP transistors, not vertical PNP transistors, can be provided in typical low-cost bipolar integrated circuit manufacturing processes, such as processes which produce the integrated circuit structure shown on page 145 of "ANALYSIS ND DESIGN OF ANALOG INTEGRATED CIRCUITS", third edition, by Paul R. Gray and Robert G. Meyer, 1993, John Wiley & Sons, Inc., entirely incorporated herein by reference. However, lateral PNP transistors are far too slow to be used in the AC signal path of a high frequency amplifier gain stage or output stage.
Many prior art operational amplifiers are manufactured using relatively low cost, well known manufacturing processes wherein the only PNP transistors (other than "substrate" PNP transistors) that can be constructed are "lateral" PNP transistors. Lateral PNP transistors have very low bandwidth compared to vertical NPN or PNP transistors. Therefore, lateral PNP transistors can not be used in the AC signal path of a high speed amplifier or output stage thereof. However, there is an unmet need for a high bandwidth amplifier output stage that includes a differential input stage which includes a pair of NPN input transistors but uses no PNP transistors, especially lateral PNP transistors, in the AC signal path. There also is a need for avoiding "shoot-through" current in the NPN pull-up transistor and the NPN pull-down transistor of such a circuit.